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| HCF4015B DUAL 4-STAGE STATIC SHIFT REGISTER WITH SERIAL INPUT/PARALLEL OUTPUT s s s s s s s s s MEDIUM SPEED OPERATION 12 MHz (Typ.) CLOCK RATE AT VDD - VSS = 10V FULLY STATIC OPERATION 8 MASTER-SLAVE FLIP-FLOPS PLUS INPUT AND OUTPUT BUFFERING HIGH NOISE IMMUNITY QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4015BEY HCF4015BM1 T&R HCF4015M013TR DESCRIPTION HCF4015B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4015B consists of two identical, independent, 4 stage serial-input/parallel-output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-TYPE, MASTER-SLAVE flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive going clock transition. The resetting of all stages is accomplished by a high level on the reset line. It is possible to expand the register to 8 stages using one HCF4015B package and to expand to more than 8 stages by using addition HCF4015Bs. PIN CONNECTION September 2002 1/10 HCF4015B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 9 6, 14 7, 15 5, 4, 3, 10 13, 12, 11, 2 8 16 SYMBOL CLOCK A CLOCK B RESET A RESET B DATA A DATA B QnA QnB VSS VDD NAME AND FUNCTION Clock Input Reset Input Data Inputs Outputs A-Stage Outpus B-Stage Negative Supply Voltage Positive Supply Voltage FUNCTIONAL DIAGRAM TRUTH TABLE CLOCK D L H X X X : Don't Care R L L L H Q1 L H Q1 L Qn Qn - 1 Qn - 1 Qn - (NO CHANGE) 0 X 2/10 HCF4015B LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C 3/10 HCF4015B DC SPECIFICATIONS Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit IL Quiescent Current A VOH High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current VOL VIH VIL IOH IOL Output Sink Current Input Leakage Current Input Capacitance 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 V V V V mA mA II Any Input Any Input 0.1 7.5 1 1 A pF CI The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 4/10 HCF4015B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns) Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 160 80 60 100 50 40 6 12 17 90 40 25 Max. 320 160 120 200 100 80 Unit CLOCKED OPERATION tPLH tPHL Propagation Delay Time (carry out or decoded out lines) tTHL tTLH Transition Time (carry out or decoded out lines) Maximum Clock Input Frequency Clock Pulse Width ns ns fCL tW 3 6 8.5 180 80 50 MHz ns 15 15 15 tr , tf (1) Clock Input Rise or Fall Time Data Setup Time s tsetup 70 40 30 35 20 15 200 100 80 100 40 30 400 200 160 ns RESET OPERATION tPLH, tPHL Propagation Delay Time ns tW Reset Pulse Width 200 80 60 ns (*) Typical temperature coefficient for all VDD value is 0.3 %/C. (1) If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed propagation delay at 15 pF and the transmission time of the carry output driving stage of the estimated capacitive load. 5/10 HCF4015B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50) WAVEFORM 1 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 6/10 HCF4015B WAVEFORM 2 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) 7/10 HCF4015B Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 8/10 HCF4015B SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 9/10 HCF4015B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 10/10 |
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